An analog delay project from Scott Swartz. All the ICs are available from Small Bear Electronics LLC or other sources.
- AD-3208 Delay Bill of Materials text file
- AD-3208 Delay PDF Schematic file
- AD-3208 Delay Layout GIF file
- AD-3208 Delay Ready-For-Transfer Printed Circuit Board Layout PDF File
AD 3208 Build Information
Copyright 2003 by Scott Swartz, all rights reserved
This project is for a true BBD analog delay. Those of you who have built or seen my PT-80 project may be wondering why I developed this one. A BBD delay does give a very slightly different character to the repeats, and with the recent availability of BL3208 BBD chips, I decided to design an old school BBD delay around them. Having designed and built both, I can tell you that the difference is subtle. The PT-80 was designed to get as close to the analog delay sound as possible, so this makes sense. If you were only building one of them, I would probably recommend the PT-80 since its simpler and cheaper to build, and offers a longer delay time, but if only BBD will do for you, here is the project.
The AD3208 is based upon the later analog delays that used the lower voltage MN32xx series of BBD chips like the Boss DM-3 and the Ibanez CD-10 Delay Champ. I picked the design elements from each as well as a few other delays to produce what I consider the best overall design.
It was designed it to accept two of the currently manufactured BL3208 chips, which give a 4096 step delay line, the same length as the DM-3 and CD-10, for a maximum delay time of about 205 milliseconds at a clock speed of 10 kHz. It can also accept two MN3205s for a 8192 step delay line, which doubles the delay time to 410 milliseconds.
Good conservative design is the clock frequency is no less than 3 times the rolloff frequency of the post delay filter, or in the case of the AD-3208, 3 kHz and a minimum clock speed of 10 kHz, which computes to 205 milliseconds. If you use two MN3205s, you will have an 8192 step BBD line which computes to 410 milliseconds at a clock speed of 10 kHz.
The clock could be run slower, but there needs to be a margin between the highest frequency you want the post delay filter to pass and the clock frequency or high pitched clock noise will be heard. I am aware that there are analog delays that claim 600 milliseconds from two MN3205s, but this would require a much steeper slope post delay filter and/or rolling off at a lower frequency in the post delay filter. Keep in mind that marketing departments have been known to stretch the truth also.
There is also a tradeoff between sound quality and length of BBD delay line.
On the AD3208 (and every other BBD Delay), if you do a experiment where you set it for 200 ms delay using two 3208s (clock of 10 kHz) and then compare that to using two 3205s with the clock at 20 kHz, the shorter delay line with 2 3208s definitely sounds better for a 200 ms delay.
The anti alias and post delay filters are the typical design used on the DM-3, CD-10, etc as you can see by cross checking the schematics. The rolloff frequencies on the AD3208 are very similar to give the classic analog delay sound.
The mixer and compander design and component values are also similar to the DM-3 and CD-10 for the same reason. They are simple and work well.
Trim Pots and Circuit Checkout
Looking at the PCB layout, you will note there are 5 trim pots. What are they for?
The 500K trim pot near the top of the PCB adjust the maximum clock speed. If you have an oscilloscope, set it so that 10 kHz is the maximum clock speed. If no scope is available, set it to its midpoint and listen for clock noise in the repeats when set to maximum delay. If there is any, adjust the trim pot for a faster clock (shorter maximum delay) speed until it is no longer audible.
The other 4 trimmers (all 10K) adjust each BBD audio output balance and bias voltage. Looking at the PCB and viewing left to right, the trim pots are:
BBD2 Balance–BBD2 Bias—BBD1 Balance?BBD1 Bias
If an oscilloscope is available, the trimmers can be set exactly for the lowest distortion. Start at the first BBD, use a 1 Vrms sine wave test signal, and adjust the first BBD?s bias and balance for the best signal to the input of the 2nd BBD. Then repeat the process checking the output of 2nd BBD.
For most people I am guessing that no scope will be available, so in that case set both balance trimmers to their midpoint, and also set both bias trimmers to their midpoint. At this point, hopefully the bias is close enough that the delay signal will pass. If not try moving both up, then both down, the one up and one down, then the opposite, and some combination should allow the delay line to work. Once bias setting are found that produce delay, set each bias to the midpoint of the range that still allows the delay signal to pass. If you experiment you will note that too high and the delay stops, also too low and the delay stops.
The audio opamp can be any decent dual opamp, such as TL072, JRC4558, NE5532, etc, etc??
The delay chips can be any combination of BL3208, MN3208, MN3205. Two 3208 chips will give a 4096 step BBD line, One 3208 chip and one 3205 chip will give a 6144 step BBD line, Two 3205 chips will give a 8192 step BBD line.
If you study the schematic closely, you will see that both the delay level and repeats signal path ?pad? the volume levels. In both cases this was done to give a better range of adjustment on the pots. For additional delay level, change the 22k resistor that connects to pin 2 of the TL072 opamp to 10k, this would be unity gain for the delay level. For additional repeats, change the 100k resistor that connects to pin 12 of the SA571 compander to a lower value, either 22k or 47k. I chose 100k for the schematic since this value gives plenty of repeats, but is low enough that the repeats pot is easy to adjust for the range of repeats I typically use.